`timescale 1 ns / 1 ps

module tb ();
    
    parameter PERIOD = 20;
    
    reg     inclk;
    reg     pll_rst;
    wire    tx_rx;
    wire    rx_r;
    wire    nrx_r;
    wire    nnrx_r;
    wire    rx_rg;
    wire    rx_fg;
    wire    rx_dg;
    wire    clk_10M;
    wire    pll_locked;
    wire    rst;
    
    assign rst = !pll_locked;
    
    reg     [9:0]   tx_data;
    reg     [9:0]   tx_data_gen;
    reg     [7:0]   frame_len; //frame length
    reg     [2:0]   frame_st;
    
    initial begin
        inclk = 1'b0;
        #(PERIOD/2);
        forever #(PERIOD/2) inclk = ~inclk;
    end
    
    initial begin
        pll_rst     = 1'b1;
        tx_data     = 0;
        #50 pll_rst = 1'b0;
    end
    
    always @ (posedge clk_10M or posedge rst) begin
        if (rst) begin
            frame_len   <= 0;
            tx_data     <= 0;
            tx_data_gen <= 0;
            frame_st    <= 0; //frame state machine
        end
        else
            case (frame_st)
                0: begin
                    frame_len <= 0;
                    frame_st  <= 1;
                    tx_data = 10'b1010_1010_10;
                    tx_data_gen <= 0;
                end
                1: begin
                    frame_len <= 0;
                    frame_st  <= 2;
                    tx_data = 10'b1010_1010_11;
                end
                2: begin
                    frame_len   <= frame_len + 1;
                    tx_data_gen <= tx_data_gen + 1;
                    tx_data     <= tx_data_gen;
                    if (frame_len == 15) frame_st < = 3;
                end
                3: begin
                    frame_st <= 0;
                    tx_data = 10'b1010_1010_10;
                end
                default: frame_st <= 3;
            endcase
    end
    
    lvds_top lvds_top_inst (
    .inclk                          (inclk),
    .pll_rst                        (pll_rst),
    .tx_data                        (tx_data),
    .tx                             (tx_rx),
    .rx                             (tx_rx),
    .clk_10M                        (clk_10M),
    .pll_locked                     (pll_locked)
    );
    
endmodule
